The present invention relates generally to qualifying integrated circuits and more particularly to a method of qualifying biased integrated circuits on a wafer level.
Many qualification tests for integrated circuits are performed on the die level once the die is mounted into a package. The packaged die is subjected to a qualifying environment and then tested. Because of the different types of housing, the temperature of the qualifying environment may be limited. Similarly, based on the number of dice from a lot which do not qualify, the decision to scrap, retest, or otherwise treat the total lot is made. Thus, if the dice can be tested at the wafer level, the expense of packaging an unacceptable lot is eliminated.
Many of the qualifying tests for environments performed at the die level require biasing of the die while being subject to a qualifying environment. Two such tests are the biased burn-in qualification and the radiation hard qualification for gamma ray radiation.
Generally for biased burn-in qualification, the individual dice, after being packaged, go through an initial testing of electrical characteristics. After the initial tests of the packaged unit, they are sent to a biased, high temperature burn-in for approximately 168 hours and then returned for testing of their electrical characteristics. Based on the type of failures occurring after the burn-in, all the dice from a given run are shelved for product engineering and failure analysis or subjected to a recycle of biased burn-in. Ultimately based on the failure rate, the whole run may be scrapped based on the failure of a few parts generally greater than five percent. If the biased burned-in testing procedure was conducted at the wafer level, the expense of packaging and re-burn-in are eliminated and an earlier decision on scrapping the run at the wafer level can be made.